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syms (symbols) and create a library 2.plb containing your. In the PCAD PCB module, run PDIF Writer and create PDFs for your library1.slb and b. Make sure that you have selected the Indented option and set the Scan Reserved Characters option before you create the files.ģ. Go to the Library pull down and select translate. Click on the Source Library button and select library1.slb. Click on the Destination Library button and enter library1 for your new library name. If you used a PCAD cross reference file to define power and heterogeneous gate information, then you will need to click on the PDIF Cross Reference button and select the file. (If you defined your power using the PWGD attribute on the gate and if you have only homogeneous components, you do not need to worry about a cross reference file.) Click on the Translate button at the bottom. Next you will get a dialog box asking about layer mapping. Unless you used some custom layers, you can click on the OK button to accept the default. Translating will continue and you will be given the option to view the log file at the end. I would recommend doing this and maybe even printing it out if you have a lot of errors.FYI- it will flag power pins as duplicates if you used the PWGD attribute on your gates. This is because it is reading the attribute for EACH gate. Technically, this is not an problem just Accel flagging something it thinks is wrong. Follow the same steps to translate your b file.
plb, it is possible that you will get a warning that looks like: Warning: The number of components pins created for AD637 does not match the number of PIN_DEF entries near line 176. Again, this is Accel flagging something that it thinks is a problem.Ĥ. Once you have your two files translated, it is now time to merge them.
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